Principal Engineer - PCIe RTL Design

About this role

Requirements

• Master’s/Bachelor’s degree in Electronics/Electrical Engineering with 18+ years of relevant experience in RTL design
• Experience on end-to-end PCIe/CXL subsystem RTL design execution and sign-off
• Proven experience delivering complex PCIe/CXL IP or subsystems from architecture through RTL closure
• Strong hands-on experience in SystemVerilog / Verilog RTL development
• Expertise in PCIe protocol architecture including link, transaction, and PHY interaction layers
• Strong understanding of CXL.io, CXL.cache, and CXL.mem architectures
• Deep knowledge of ARM-based SoC integration and AMBA protocols (AXI-4, CHI, ACE)
• Experience designing high-performance, low-latency data paths and handling ordering, coherency, and error mechanisms

Responsibilities

• Own and drive PCIe/CXL subsystem micro architecture definition, RTL implementation, and integration
• Collaborate closely with Architecture teams to translate requirements into robust RTL designs
• Work with Design Verification teams on test-plan reviews, debug, and coverage closure
• Partner with Physical Design and DFT teams to ensure PD-friendly and DFT-ready RTL
• Support silicon bring-up and post-silicon debug, working with firmware and validation teams
• Drive design quality improvements, coding best practices, and reuse across projects
• Participate in design reviews, milestone reviews, and cross-functional technical discussions
• Mentor junior designers and provide technical leadership within the PCIe/CXL design domain

Benefits

• Workstyle within an environment of shared collaboration, transparency, and inclusivity
• Tools and resources to succeed in doing work that matters
• Opportunities to grow and develop with the company